1. Field of the Invention
The present invention relates to an instrumentation amplifier that amplifies output signals of various sensors or the like.
2. Description of Related Art
In the related art, an instrumentation amplifier has been used to receive an output signal of various sensors or the like with high impedance and to amplify the output signal with high accuracy (for example, see Refet Firat Yagicioglu, A 200 uW Eight-Channel EEG Acquisition ASIC for Ambulatory EEG Systems, IEEE Journal Solid-State Circuits, Vol. 43, No. 12, December, 2008, pp. 3025-3038). A configuration of the instrumentation amplifier described in this document will be described below.
FIG. 3 shows the configuration of the instrumentation amplifier described in Refet Firat Yagicioglu, A 200 uW Eight-Channel EEG Acquisition ASIC for Ambulatory EEG Systems, IEEE Journal Solid-State Circuits, Vol. 43, No. 12 December, 2008, pp. 3025-3038. As shown in FIG. 3, an instrumentation amplifier 100 includes a first input stage 101, a second input stage 102, a first resistor R1, and a second resistor R2.
The first input stage 101 shifts a level of a positive input voltage (Vinp) applied to a positive input terminal and outputs the level-shifted voltage. The second input stage 102 shifts a level of a negative input voltage (Vinn) applied to a negative input terminal and outputs the level-shifted voltage. The first resistor R1 is connected between the first input stage 101 and the second input stage 102 and generates a differential current (ΔIin=ΔVin/R1) corresponding to the voltage of a difference (ΔVin=Vinp−Vinn) between the output voltage of the first input stage 101 and the output voltage of the second input stage 102. The second resistor R2 is connected between the first input stage 101 and the second input stage 102 and converts the differential current ΔIin generated by the first resistor R1 into a first output voltage (Voutp) and a second output voltage (Voutn).
The first input stage 101 includes transistors M1 and M2, current sources I1, I2, and I3, and a level shift circuit LS1. The gate terminal of the transistor M1 is connected to the positive input terminal, and the source terminal of the transistor M1 is connected to a first end of the first resistor R1. A first end of the current source I1 is connected to the source terminal of the transistor M1 and the first end of the first resistor R1, and a second end of the current source I1 is connected to the highest potential. The drain terminal of the transistor M2 is connected to the source terminal of the transistor M1, the first end of the first resistor R1, and the first end of the current source I1, and the source terminal of the transistor M2 is connected to a negative output terminal. A first end of the current source I2 is connected to the source terminal of the transistor M2 and a first end of the second resistor R2, and a second end of the current source I2 is connected to the lowest potential. A first end of the current source I3 is connected to the drain terminal of the transistor M1, and a second end of the current source I3 is connected to the lowest potential. A first end of the level shift circuit LS1 is connected to the drain terminal of the transistor M1, and a second end of the level shift circuit LS1 is connected to the gate terminal of the transistor M2.
The second input stage 102 includes transistors M3 and M4, current sources I4, I5, and I6, and a level shift circuit LS2. The gate terminal of the transistor M3 is connected to the negative input terminal, and the source terminal of the transistor M3 is connected to a second end of the first resistor R1. A first end of the current source I4 is connected to the source terminal of the transistor M3 and the second end of the first resistor R1, and a second end of the current source I4 is connected to the highest potential. The drain terminal of the transistor M4 is connected to the source terminal of the transistor M3, the second end of the first resistor R1, and the first end of the current source I4, and the source terminal of the transistor M4 is connected to a positive output terminal. A first end of the current source I5 is connected to the source terminal of the transistor M4 and a second end of the second resistor R2, and a second end of the current source I5 is connected to the lowest potential. A first end of the current source I6 is connected to the drain terminal of the transistor M3, and a second end of the current source I6 is connected to the lowest potential. A first end of the level shift circuit LS2 is connected to the drain terminal of the transistor M3, and a second end of the level shift circuit LS2 is connected to the gate terminal of the transistor M4.
The operation of the instrumentation amplifier 100 will be described below. When the positive input voltage (Vinp) is applied to the gate terminal of the transistor M1, the first input stage 101 outputs a voltage of the sum of the positive input voltage (Vinp) and the gate-source voltage (Vgs) of the transistor M1. This voltage is output from the first input stage 101 and is applied to the first end of the first resistor R1. When the negative input voltage (Vinn) is applied to the gate terminal of the transistor M3, the second input stage 102 outputs a voltage of the sum of the negative input voltage (Vinn) and the gate-source voltage (Vgs) of the transistor M3. This voltage is output from the second input stage 102 and is applied to the second end of the first resistor R1. Accordingly, the voltage of the difference (ΔVin=Vinp−Vinn) between the positive input voltage (Vinp) and the negative input voltage (Vinn) is supplied to the first resistor R1.
The first resistor R1 generates the differential current (ΔIin=ΔVin/R1) corresponding to the differential voltage (ΔVin=Vinp−Vinn) and supplies an operating current from the current sources I1 and I4 to the transistors M2 and M4 based on the differential current (ΔIin=ΔVin/R1). The current sources I2 and I5 sink the operating current supplied to the transistors M2 and M4 and the current sources I3 and I6 keep the operating current of the transistors M1 and M3 constant.
The current source I1 supplies the operating current set by the current source I3 to the transistor M1 and supplies the operating current corresponding to the differential current (ΔIin=ΔVin/R1) generated in the first resistor R1 to the transistor M2. The current source I4 supplies the operating current set by the current source I6 to the transistor M3 and supplies the operating current corresponding to the differential current (ΔIin=ΔVin/R1) generated in the first resistor R1 to the transistor M4. The second resistor R2 converts the differential current (ΔIin=ΔVin/R1) generated in the first resistor R1 into a first output voltage (Voutp) and a second output voltage (Voutn).
More specifically, the differential current (ΔIin=ΔVin/R1) is a part of the operating current supplied from the current sources I1 and I4 and is expressed by Equations (1) to (3). In Equations (1) to (3), the operating currents supplied from the current sources I2, I3, I5, and I6 are Ibias, the operating currents supplied from the current sources I1 and I4 are 2Ibias, the operating current of the transistor M2 is Im2, and the operating current of the transistor M4 is Im4.
If positive input voltage (Vinp)>negative input voltage (Vinn),
                                          I                          m              ⁢                                                          ⁢              4                                =                                    I              bias                        +                          Δ              ⁢                                                          ⁢                              I                                  i                  ⁢                                                                          ⁢                  n                                                                    ⁢                                  ⁢                              I                          m              ⁢                                                          ⁢              2                                =                                    I              bias                        -                          Δ              ⁢                                                          ⁢                              I                                  i                  ⁢                                                                          ⁢                  n                                                                    ⁢                                  ⁢                              Δ            ⁢                                                  ⁢                          I                              i                ⁢                                                                  ⁢                n                                              =                                                    Vinp                -                Vinn                                            R                1                                      =                                                            Δ                  ⁢                                                                          ⁢                                      V                                          i                      ⁢                                                                                          ⁢                      n                                                                                        R                  1                                            >              0                                                          (        1        )            
If positive input voltage (Vinp)<negative input voltage (Vinn),
                                          I                          m              ⁢                                                          ⁢              4                                =                                    I              bias                        -                          Δ              ⁢                                                          ⁢                              I                                  i                  ⁢                                                                          ⁢                  n                                                                    ⁢                                  ⁢                              I                          m              ⁢                                                          ⁢              2                                =                                    I              bias                        +                          Δ              ⁢                                                          ⁢                              I                                  i                  ⁢                                                                          ⁢                  n                                                                    ⁢                                  ⁢                              Δ            ⁢                                                  ⁢                          I                              i                ⁢                                                                  ⁢                n                                              =                                                    Vinp                -                Vinn                                            R                1                                      =                                                            Δ                  ⁢                                                                          ⁢                                      V                                          i                      ⁢                                                                                          ⁢                      n                                                                                        R                  1                                            <              0                                                          (        2        )            
If positive input voltage (Vinp)=negative input voltage (Vinn),
                                          I                          m              ⁢                                                          ⁢              4                                =                                    I                              m                ⁢                                                                  ⁢                2                                      =                          I              bias                                      ⁢                                  ⁢                              Δ            ⁢                                                  ⁢                          I                              i                ⁢                                                                  ⁢                n                                              =                                                    Vinp                -                Vinn                                            R                1                                      =                                                            Δ                  ⁢                                                                          ⁢                                      V                                          i                      ⁢                                                                                          ⁢                      n                                                                                        R                  1                                            =              0                                                          (        3        )            
Since all the operating currents (Im2 and Im4) supplied to the transistors M2 and M4 are sunken by the current sources i2 and I5, the entire differential current (ΔIin=ΔVin/R1) is supplied to the second resistor R2. Accordingly, when the voltage of the difference between the first output voltage (Voutp) and the second output voltage (Voutn) is defined as ΔVout, Equations (4) and (5) are obtained.
If positive input voltage (Vinp)>negative input voltage (Vinn),
                                          V            outp                    =                                    Δ              ⁢                                                          ⁢                              I                                  i                  ⁢                                                                          ⁢                  n                                            ×                              R                2                                      =                                                            R                  2                                                  R                  1                                            ⁢              Δ              ⁢                                                          ⁢                              V                                  i                  ⁢                                                                          ⁢                  n                                                                    ⁢                                  ⁢                              V            outn                    =                                                    -                Δ                            ⁢                                                          ⁢                              I                                  i                  ⁢                                                                          ⁢                  n                                            ×                              R                2                                      =                                          -                                                      R                    2                                                        R                    1                                                              ⁢              Δ              ⁢                                                          ⁢                              V                                  i                  ⁢                                                                          ⁢                  n                                                                    ⁢                                  ⁢                              Δ            ⁢                                                  ⁢                          V              out                                =                                                    V                outp                            -                              V                outn                                      =                          2              ⁢                                                R                  2                                                  R                  1                                            ⁢              Δ              ⁢                                                          ⁢                              V                                  i                  ⁢                                                                          ⁢                  n                                                                                        (        4        )            
If positive input voltage (Vinp)<negative input voltage (Vinn),
                                          V            outp                    =                                                    -                Δ                            ⁢                                                          ⁢                              I                                  i                  ⁢                                                                          ⁢                  n                                            ×                              R                2                                      =                                          -                                                      R                    2                                                        R                    1                                                              ⁢              Δ              ⁢                                                          ⁢                              V                                  i                  ⁢                                                                          ⁢                  n                                                                    ⁢                                  ⁢                              V            outn                    =                                                    -                Δ                            ⁢                                                          ⁢                              I                                  i                  ⁢                                                                          ⁢                  n                                            ×                              R                2                                      =                                                            R                  2                                                  R                  1                                            ⁢              Δ              ⁢                                                          ⁢                              V                                  i                  ⁢                                                                          ⁢                  n                                                                    ⁢                                  ⁢                              Δ            ⁢                                                  ⁢                          V              out                                =                                                    V                outp                            -                              V                outn                                      =                                          -                2                            ⁢                                                R                  2                                                  R                  1                                            ⁢              Δ              ⁢                                                          ⁢                              V                                  i                  ⁢                                                                          ⁢                  n                                                                                        (        5        )            
Therefore, the instrumentation amplifier 100 amplifies the voltage of the difference (ΔVin=Vinp−Vinn) between the positive input voltage (Vinp) and the negative input voltage (Vinn) by 2(R2/R1) times based on the resistance ratio of the first resistor R1 and the second resistor R2.
In the instrumentation amplifier 100, it is necessary to set the current supplied from the current sources I1 and I4 to 2Ibias and to set the current sunken by the current sources I2, I3, I5, and I6 to Ibias. In this case, the sum of currents flowing from the highest potential to the current sources I1 and I4 is equal to the sum of currents flowing from the current sources I2, I3, I5, and I6 to the lowest potential. The differential current (ΔIin=ΔVin/R1) flowing in the first resistor R1 and the differential current (ΔIin=ΔVin/R1) flowing in the second resistor R2 have the same magnitude and opposite directions. Accordingly, a current flowing from the positive output terminal to the outside or a current flowing from the outside to the positive output terminal is substantially zero. Similarly, a current flowing from the negative output terminal to the outside or a current flowing from the outside to the negative output terminal is substantially zero.
Accordingly, output current capability indicating the current flowing from the positive output terminal and the negative output terminal of the instrumentation amplifier 100 to the outside or the current flowing from the outside to the positive output terminal and the negative output terminal of the instrumentation amplifier 100 is substantially zero. As a result, when impedance of a load or a circuit connected to the rear stage of the instrumentation amplifier 100 is not set to be very large, the output voltage is attenuated.
More specifically, as shown in FIG. 4, when a capacitive feedback variable-gain circuit 200 is connected to the rear stage of the instrumentation amplifier 100, the input impedance of the variable-gain circuit 200 becomes a small value (i/jωc) due to the impedance of the capacitance (c) on an input side and the output voltage of the instrumentation amplifier 100 is attenuated. Accordingly, as shown in FIG. 5, it is necessary to insert a buffer circuit 300 between the instrumentation amplifier 100 and the variable-gain circuit 200 to accurately transmit the output voltage of the instrumentation amplifier 100 to the variable-gain circuit 200.
However, when the buffer circuit 300 is inserted between the instrumentation amplifier 100 and the variable-gain circuit 200, a voltage range to be transmitted to the variable-gain circuit 200 is narrowed by an offset voltage of the buffer circuit 300 (the gate-source voltage of the transistor in the example shown in FIG. 5).